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Privacy & Cookies: This site uses cookies. By continuing to use this website, you agree to their use. To find out more, including how to control cookies, see here: Cookie PolicyThe present invention relates to a dynamic random access memory (DRAM) cell structure. More specifically, the present invention relates to a method for forming a DRAM cell having a vertical transistor.
Memory chips are often constructed with a plurality of memory cells. Each memory cell may be constructed with a single access transistor coupled to a capacitor. The access transistor serves as a switch for the capacitor. One side of the capacitor is coupled to a common node which serves as a reference for the memory cell. Thus, the memory cell is capable of storing a logic state based on the relative charge of the capacitor.
In order to construct a high-density DRAM chip, it is desirable to reduce the size of each cell as much as possible. One way to accomplish this reduction is to construct a DRAM cell with a vertical transistor, instead of a conventional planar transistor. The vertical transistor is oriented parallel to the substrate which is convenient to the formation of other memory cell structures.
While vertical transistors are desirable for their compact construction, they also present unique difficulties. For example, vertical transistors require a gate dielectric layer having a charge which is greater than that used for a planar transistor. Thus, the vertical transistor must have a gate oxide which is thicker than a conventional planar transistor.
The thick gate oxide layer must be accurately formed to prevent any leakage from the gate electrode to the substrate. However, the thick oxide layer can also create a problem in the formation of an adjacent capacitor.
In a conventional planar transistor, the source/drain regions are formed in the substrate beneath the gate electrode. Thus, the source/drain regions are generally formed at the bottom of the gate electrode. The capacitor is then formed above the gate electrode and the source/drain regions.
In a vertical transistor, the source/drain regions are formed in the substrate in a direction orthogonal to the gate electrode. Thus, the source/drain regions are generally formed at the side of the

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